1. Field of the Invention
The present invention relates to a semiconductor device that is provided with memory, and more particularly to a semiconductor device that is provided with a product code ECC (Error Checking and Correcting) circuit for correcting errors in memory, and to a method of testing such a device.
2. Description of the Related Art
Of the various methods that are used in a dynamic semiconductor memory device that requires a refresh operation to hold data, the Super Self Refresh (SSR) technology can extend the refresh cycle to as much as approximately one second when the ambient temperature Ta is 85° C., by both arranging an ECC circuit on a semiconductor memory device and then encoding the entire chip area at the time of entry to a low-consumption power mode and implementing a correction operation of the entire chip area at the time of exit from the low-consumption power mode. The SSR technology is disclosed in, for example, Japanese Patent Laid-Open Publication No. 2002-56671 (JP, P2002-56671A).
FIG. 1A shows the configuration of a semiconductor memory device of the prior art that uses the SSR technology, and FIG. 1B gives a schematic representation of the configuration of a memory cell array that is provided with a product code parity bit area.
The two codes C1 and C2 are a (n1, k1) code and a (n2, k2) code, respectively; and k1*k2 information points are encoded as a two-dimensional arrangement of k1 rows and k2 columns by encoding k1 information points of each column by code C1 and encoding k2 information points of each row by code C2 to obtain a code word having an overall length of n1*n2. Code that is obtained by this type of encoding is linear (n1*n2, k1*k2) code and is referred to as the product code of codes C1 and C2.
As shown in FIG. 1A, the semiconductor memory device is provided with a plurality of banks 100, with a plurality of encoders/decoders 101 and a plurality of write buffer/main buffers 102 being provided for each bank 100. Encoder/decoders 101 are connected to SDRAM (Synchronous DRAM) interface 103; and SDRAM interface 103 is connected to ECC controller 104. In this case, each write buffer/main buffer 102 is provided between a corresponding encoder/decoder 101 and bank 100. The area marked by diagonal lines in FIG. 1A indicates one representative memory cell array. Bank 100 is provided with a plurality of such memory cell arrays.
Focusing next on each memory cell array, as shown in FIG. 1B, a memory cell array has 1024×1024 cells for storing information bits that are arranged two-dimensionally, a storage area of parity bits in the vertical direction (code #1), and a storage area of parity bits in the row direction (code #2), whereby product code is stored. Parity bits in the vertical direction are (1040, 1024) Hamming code, and parity bits in the row direction are (1040, 1024) Hamming code.
Explanation next regards the SSR procedure in a semiconductor memory device of this type with reference to FIG. 2.
First, entry is made to SSR in Step S1, following which the entire area of the bank is encoded in Step S2. In this encoding, cell areas that store information bits are subjected to prescribed error correction encoding, and the results of this encoding are stored in the cell areas of the information bits and in the cell areas of the parity bits, following which the bank is subjected to a refresh operation in Step S3, and determination carried out in Step S4 whether to exit SSR. If SSR is not exited at this point, the process returns to Step S3 and the refresh operation is again carried out. Alternatively, if it is determined to exit SSR in Step S4, the SSR exit process is carried out in Step S5, and all areas are encoded in Step S6. The encoding implemented in Step S6 corresponds to the correction operation.
FIG. 3 is a graph showing the improvement in the refresh cycle brought about by the use of the SSR technology. In FIG. 3, the horizontal axis shows the retention time (i.e., refresh cycle) tREF, and the vertical axis shows the error rate (%). The rate of occurrence of defective bits is used as the error rate. In the figure, the DRAM error rate is normal DRAM error rate, i.e., the error rate of DRAM that does not employ the SSR technology.
The points indicated by the broken line in FIG. 3 show the error rate in a semiconductor memory device that employs the SSR technology. At tREF=1 second, approximately 100 defective bits occur due to fluctuation in retention time, and an error pattern occurs in which correction by SSR is not possible. FIG. 3 shows an error rate of 1 bit (approximately 1×10−7) at tREF=0.1 seconds and below.
FIG. 4 shows the state of occurrence of defective bits in DRAM due to fluctuation of the retention time tREF in the semiconductor memory device that employs SSR technology. In FIG. 4, the horizontal axis represents time, and the vertical axis represents the error rate (%). When tREF is equal to or greater than 0.1 second, the DRAM error rate rises, and results in drastic further occurrence of additional errors after shipment.
Essentially, a semiconductor memory device must be developed in which the error rate does not increase when tREF is equal to or greater than 0.1 second, and in which the occurrence of additional errors following shipment is suppressed.
FIG. 5 is a flow chart for explaining the process of the prior art for remedying defective cells in a semiconductor memory device that employs the SSR technology.
First, in Step S11, writing to all bits is carried out in the pattern “ALL Physical 1” i.e., a pattern of values in which the logical value is “1” when the cells are read. After writing, encoding which uses the product code is carried out in Step S12, following which refresh operation is repeated at a cycle of 1 second in Step S13.
Next, in Step S14, data are read from the memory cell array and decoded, and in Step S15, a pass/fail determination is carried out for the data that have been read to generate fail information. The fail bits are then remedied by replacement by means of redundant cells.
FIG. 6 is a view for explaining the correction operation by product code. Here, a case is explained in which a correction operation by means of ECC that uses product code enables fail bits to be saved without implementing replacement by redundant cells. FIG. 6 shows a memory cell array that contains fail bits. In the figure, “x” indicates a fail address or a fail cell. In addition, a plot of the arrangement of fail cells or fail bits in a memory cell array is referred to as a “fail map.”
Cell array 306A that includes fail cells is subjected to single-bit error correction by code #1. Because 2 or more points of fail bits per column cannot be corrected at this time, fail map 306B is obtained as the cell array data following correction. The memory cell array shown in this fail map 306B is
subjected to single-bit error correction by code #2. As shown in FIG. 6, error correction by means of product code results in PASS by correction by means of code #2 and remedying by redundancy is not necessary. In other words, it is possible to carry out error correction of the defective cells of each row by error correction by means of code #2, whereby remedying by redundant cells becomes unnecessary.
In contrast, FIG. 7 gives a schematic representation of the operations for a case in which error correction by ECC is not possible and replacement by redundant cells, i.e., the redundancy remedy of the prior art, becomes necessary.
Cell array 307A that includes fail cells is subjected to the single-bit error correction by means of code #1 as described hereinabove to obtain the fail map 307B, and then memory cell array that is shown in fail map 307B is subjected to single-bit error correction by means of code #2. Since correction is not possible for cases of two fail bits per row, fail bits (defective cells) in fail map 307C in this case become the object of remedy by means of redundant cells.
When the defect remedy method of the prior art is used, however, defective bits occur due to fluctuation in retention time following shipment of the DRAM product as shown by “additional errors following shipment” in FIG. 4, and these additional error bits cause a drastic increase, for example, in the order of ten, in the market defective rate, i.e., the defective rate following shipment.
FIG. 8 gives a schematic representation of both an uncorrectable pattern that can be detected in the process of wafer inspection before shipment and a pattern that was determined to be correctable in the process of wafer inspection but that becomes uncorrectable due to fluctuation in retention time that occurs after shipment. As shown in FIG. 8, memory LSI (large-scale integration) that allows correction of defective bits by product code ECC includes both a pattern of bits that are already uncorrectable and a pattern of bits that have become uncorrectable by the addition of single-bit fail bits. A cell which is correctable at the time of wafer inspection, but will become uncorrectable by addition of a single-bit fail bit is referred to as a potential defect cell.